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Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- Without any timing constraints, it will assume you want an FMax of 1000 Mhz, and may try rather hard. Set up timing contraints for your design may make it's life easier. --- Quote End --- Thank you Tricky! Indeed, in the mean time I added some timing constraints (not all, for now) and the compilation is quite faster. My first goal was only to see if the design could fit in the FPGA (the board is not yet designed, we could still chose another FPGA...), so my project is not complete.