Version control for the Quartus project

1. Yes. They define all the settings like pinouts etc. SDC files will have timing info.

2. What IPs are you talking about? IIRC, the megawizard (or whetever it is now) only outputs HDL for standard elements (PLLS, rams, fifos etc) that are just wrappers around the altera_mf library. So you only need these wrapper files. it should detect its a megawizard output when compiling (i think it dumps a load of data into the HDL comments).

But you can avoid these IPs almost entirely by using

i) Inference (so you can write behavioural, mostly portable VHDL code) http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf

ii) using the altera_mf library yourself (instantiate the megawizard IPs without using the megawizard). For example, the alsyncram megafunction can be found in quartus help. http://quartushelp.altera.com/13.0/mergedprojects/hdl/mega/mega_file_altsynch_ram.htm . The parameter list are the generics to the component.

3. As I said above, for most things altera generates HDL with metadata, rather than Xilinx's annoying default of generating cores. So its all HDL and text and human readible.