Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Verilog with ANSI-style regs, non-zero initial value is not synthesised correctly!

Hi, We raised this with Altera and had it confirmed in Quartus V13, but the issue is not fixed in 13.sp1 so I thought I would raise awareness here in the hope it might save anyone else debugging ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I'm sure everyone who's bitten by this learns the hard way. Probably cost us about 20 hours engineering time to go from malfunction all the way back through reproducing in post-synthesis then observing the difference vs. original HDL synthesis. Really is a nasty one to catch you out if you happen to drift a bit to much into the "new style" Verilog spec.