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Altera_Forum
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12 years ago

Verilog with ANSI-style regs, non-zero initial value is not synthesised correctly!

Hi, We raised this with Altera and had it confirmed in Quartus V13, but the issue is not fixed in 13.sp1 so I thought I would raise awareness here in the hope it might save anyone else debugging ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yeah, I've updated to indicate it's clocked and driven yreg in the workaround. The example posted in the service request was somewhat more detailed. Thanks.