Honored Contributor
Honored ContributorVerilog initially used the term "Register" for the reg data type. However, the 1364-2001 LRM began using the term "Variable" because these things did not always represent a synthesizable register in RTL. Verilog allows you to make procedural assignments to variables (and synthesis tools may further limit where you can make procedural assignments to variables) A variable behaves like a variable in any other programming language: you make an assignment to that variable, and the value of that assignment holds in the variable until the next procedural assignment. Variables of type reg have 4-states; 0, 1, X, and Z.
Wires or networks(nets) are continuously driven by the outputs of modules, primitives like nand gates and continuous assign statements. wires can have 0, 1 or more drivers, and can never be procedurally assigned. Verilog wires have a complex system for resolving multiple drivers based on 120 states/strengths. Anytime the value of a driver changes, Verilog has to look at the values of all the other drivers on the network and uses a built-in resolution function for determining the result. For example, if you have a pull-up driving a wire and and another continuous assignment driving a Strong-0, the wire will resolve to 0. If the continuous assigment starts driving a Z, the wire will go to the Pull-1 state. The SUPERLOG language, which was the predecessor to SystemVerilog, created the logic datatype that was originally slightly different from reg in that it allowed a single continuous assignments to logic variables in place of any procedural assignments. With only one driver, no strengths or resolution functions are needed, and whatever strength is being driving to the variable will result in a simple 4-state value. Eventually, the SystemVerilog committee decided to make reg have the exact same functionally logic and now the two terms are synonyms for each other. I would consider the term reg deprecated and all new SystemVerilog code should just use logic.
