Verilog, SV- data types confusion (logic, reg, wire...)

It's a bit of a mess.

"reg" and "logic" are the original Verilog types.

"reg" can be assigned within from "always" blocks (weather they describe sequential or combinatory logic), and can only have one driver.

"wire" are assigned with "assign" or a module port and can have multiple drivers.

"logic" is an addition in SystemVerilog.

It can be driven from either "always", "assign" or module port but can't be driven by multiple drivers.

So, if restricted to Verilog, I'll use "reg" and "wire" according to the restrictions above.

If I'm using SystemVerilog, I'll use "logic" for pretty much everything.

I'll use "wire" when I need multiple drivers. Within a FPGA, there's zero place for that, I only use it for testbenches where I need to model a bus with multiple devices.