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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog simulation

I wonder if what I've in mind is possible. Imagine I've a 64bit counter that rolls to 0 when the count is 64'hFFFFFFFFFFFFFF0. The counter is described in Verilog code. The counter has no s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I solved the problem using Verilog.

The command that should be used is 'force' followed by 'release'.

Here's a snmipset of the code: 

 
initial
begin
reset=1;{read_write, ready, write_OK}=3'b000;# period;
reset=0;{read_write, ready, write_OK}=3'b000;# (2*period);
{read_write, ready, write_OK}=3'b010;# period;
{read_write, ready, write_OK}=3'b001;# period;
// ac_state is the name of the internal node
force UUT.ac_state = 5'b00000;# period; 
release UUT.ac_state;# (3*period)
$stop;
end
endmodule