Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Verilog real functions and compile time

I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Maybe you can use a simple text macro instead of a function?

module math_real_test (y);

output [31:0] y;

`define f_real 5.74857 * (0.7071 + `x)

`define x 1.2

assign y = 4096 * `f_real;

endmodule