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Altera_Forum's avatar
Altera_Forum
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17 years ago

Verilog real functions and compile time

I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Ok, now I understand what you want to do. Try this:

module math_real_test (y);

output [31:0] y;

function [31:0] f_real;

input [31:0] x ;

f_real = 5.74857 * (x + 0.7071) ;

endfunction

assign y = 4096 * f_real(1);

endmodule