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Altera_Forum
Honored Contributor
Honored ContributorVerilog real functions and compile time
I am trying to write a Verilog module and synthesize it using Quartus II 8.0, but I am running into some issues. I have a function which returns a real value, and takes in real values for argum...
Altera_ForumHonored Contributor
Honored ContributorSorry, but that's not clear to me. Does the module output a 16 bit vector or a real variable? Real variables cannot be uses for synthesis, thats true.
