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Altera_Forum
Honored Contributor
Honored ContributorVerilog Question with Quartus.
I use verilog in my Quartus designs and like using the "parameter" statements. When I design a new module and use the statements everything works fine. My problem is when I change the value of the ...
Altera_ForumHonored Contributor
Honored ContributorI had a similar problem when I converted a Verilog module to a symbol for use on a schematic. Changes to the parameter file were not updated in the symbols. Are you using symbols?
