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Altera_Forum
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16 years ago

Verilog: is else statement mandatory

I'm reviewing a program written by another developer, and have noticed that they frequently leave out the final else in if/else statements, nor do they always assign values to all variables from one ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Thanks for the clarifications... for the most part the blocks are all part of synchronous (@posedge clock) always blocks.

I'll only enforce the more verbose style in combinatorial blocks.