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Is there anything strictly dangerous about doing so in Quartus Verilog? Is is free to treat unspecified variables as "DON'T CARE", or will it enforce that the value not change?
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It will enforce a no change. We are all assuming this is part of a synchronous clocked process. If so, then this is ok in most cases.
If it is combinatorial logic, then it might be dangerous because it would normally produce an async latch.
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In both cases, the synthesis tool has to decide whether to implement the combinatorial logic as a clock enable (if the device has such a thing) or as an always enabled register with feedback from the register output.
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I read this paragraph, and it sounds a bit misleading to me.
In most modern ASIC technologies, both things are actually the same. In other words, clock enable is usually implemented as a mux with the register feedback.
When talking about an FPGA, matters are different. e.g., in most Altera families, the clock enable is a LAB wide signal. Then both synthesis methods, clock enable or LUT based mux, are indeed different.
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