Verilog: is else statement mandatory

The code is perfectly legal and safe. Assuming there were no other logic controlling the value and compare signals the code be rewritten to look like:

if(value>=compare) begin
   value      <=0;
   compare <= compare;
end else begin
   value      <= value; 
   compare <= compare - 1;
end

It would have the exact same meaning as the original code. The latter is merely more verbose and adds no value.

Now if you want to get very technical, the two blocks of code can produce different synthesis results (though not in Quartus). I submit that the original code is actually more efficient. In both cases, the synthesis tool has to decide whether to implement the combinatorial logic as a clock enable (if the device has such a thing) or as an always enabled register with feedback from the register output.

Jake