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Altera_Forum
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16 years ago

Verilog: is else statement mandatory

I'm reviewing a program written by another developer, and have noticed that they frequently leave out the final else in if/else statements, nor do they always assign values to all variables from one ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

In every language, if the condition is true then action1 else action2.

you are free to use if only or add else or else if depending on what you want to do in each case.

If a variable is not assigned in a construct then it retains its value. In synthesisable HDL, this means a latch or register(if clked).