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Altera_Forum
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14 years ago

Verilog hierarchical path names in Quartus

Hello all, I am trying to build a design containing hierarchical verilog paths in Quartus, for example: wire usr_led = foo.bar.signalname; but Quartus gives me: Error (10207): Verilog HDL ...
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Altera_Forum
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13 years ago

I believe those are both simulation tools(not sure about the second). Modelsim also supports it. It's extremely useful in simulation, since you can bring out signals for watching and analyzing very quickly. I would be surprised if any major simulations tools didn't support it, but I'm curious about synthesis tools.