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Altera_Forum
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14 years ago

Verilog hierarchical path names in Quartus

Hello all, I am trying to build a design containing hierarchical verilog paths in Quartus, for example: wire usr_led = foo.bar.signalname; but Quartus gives me: Error (10207): Verilog HDL ...
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Altera_Forum
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13 years ago

SignalTap is not done in HDL, but instead has its own GUI and "hidden infrastructure". So yes, it does probe signals without having to hook up to them directly, but it can't be used for general logic. Does anyone know of other synthesis tools that support hierarchical names? Just curious.