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Altera_Forum
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14 years ago

Verilog hierarchical path names in Quartus

Hello all, I am trying to build a design containing hierarchical verilog paths in Quartus, for example: wire usr_led = foo.bar.signalname; but Quartus gives me: Error (10207): Verilog HDL ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I did not think this was possible, and from your test it doesn't seem to work, but would be very happy if it did. (This could be very confusing if used incorrectly, but debug is a perfect case...) If nobody responds, please file an SR and let us know the result?