Verilog HDL question

Actually, it's OK to declare an input as "wire".

In fact, the reason you don't need to do it is because, by default, Verilog assumes everything is a wire. Even undeclared variables...

Some of us like to begin their Verilog modules with "`default_nettype none" to make sure the compiler yields an error for undeclared stuff.

In such case, you need to explicitly declare the inputs as wires.

In general, my Verilog looks something like:

`default_nettype none

module foo (

input wire [1:0] a,

output reg [1:0] b,

output wire [1:0] c

);

...

endmodule