Verilog HDL question

for an input like A you do not need to use wire, in fact i haven't seen that yet so it could be possible or even not allowed

wires can only be used for outputs (as far as i know)

you could also write

module dummy (

input A,

output reg [3:0] B

);

i personaly does not declared like my example as this could lead into problems when using wires and assigns.

so i prefer this one

module dummy ( A,B,C );

input A;

output reg [3:0] B;

output [3:0] C;

wire [3:0] C;

assign C=B;

endmodule