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AEsqu's avatar
AEsqu
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4 years ago

verilog define in the .qsf or .tcl for quartus?

Hello, I use this command in a Synplify project to define for a verilog check code translation: set_option -hdl_define -set {"WITH_TH"} This is then picked in verilog: `ifdef WITH_TH c...
AEsqu's avatar
AEsqu
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4 years ago

Hi Ean,

your answer is about creating a vqm file,

which is not the question.

Anyway, I used what I proposed after as a workaround.

  • YEan's avatar
    YEan
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    4 years ago

    Hi ,

    I’m glad that your issue has been resolved. I'll now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts.

    Thank you.

    Regards,

    Ean