Forum Discussion
verilog define in the .qsf or .tcl for quartus?
Hello,
I use this command in a Synplify project to define for a verilog check code translation:
set_option -hdl_define -set {"WITH_TH"}
This is then picked in verilog:
`ifdef WITH_TH
code line here will be picked
`endif
endmodule
My question:
How to do it for Quartus?
I'm used to the
set_parameter -name ...
but that is not applicable in this case.
Thanks!
4 Replies
- AEsqu
Contributor
Is this the only way?
Create a new verilog file with this inside:
`define WITH_TH
and add this file in the quartus .qsf
- YEan
Contributor
Hi
You may refer this guide https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/eda/synthesis/synplicity/eda_pro_synplty_generate_vqm.htm . It seems like you have to include .vqm and .tcl files in it.
Thanks,
Ean
- AEsqu
Contributor
Hi Ean,
your answer is about creating a vqm file,
which is not the question.
Anyway, I used what I proposed after as a workaround.