AEsqu
Contributor
4 years agoverilog define in the .qsf or .tcl for quartus?
Hello,
I use this command in a Synplify project to define for a verilog check code translation:
set_option -hdl_define -set {"WITH_TH"}
This is then picked in verilog:
`ifdef WITH_TH
code line here will be picked
`endif
endmodule
My question:
How to do it for Quartus?
I'm used to the
set_parameter -name ...
but that is not applicable in this case.
Thanks!