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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog Constants/Paremters accross Verilog Files?

Hi Guys, I'm teaching myself verilog atm, (i've done small VHDL before). My question is: how can i define and share constants accross .v files? For instance in C: Say you want to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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It might also be worth looking into packages.

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This would be the standard means in VHDL designs. I'm not quite sure which Verilog element you're adressing with "packages". As far as I'm aware of, there's no suitable Verilog option besides included file constants and module parameters passed through the hierarchies.