Verilog Constants/Paremters accross Verilog Files?

It might also be worth looking into packages. Although the `include is easy, I've found it more difficult to debug, as the file is read in "behind the scenes" and so it's hard to figure out what's going on. I think packages are more formal. (I also prefer formally passing the parameter in alongside the ports whenever possible). I think you can get by with both, and I don't do enough coding to really have a good handle, but would be curious if others had an opinion on the best way to handle this?