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Altera_Forum
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15 years ago

Verilog Constants/Paremters accross Verilog Files?

Hi Guys, I'm teaching myself verilog atm, (i've done small VHDL before). My question is: how can i define and share constants accross .v files? For instance in C: Say you want to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It is possible to do so. As fvm (http://www.alteraforum.com/forum/member.php?u=3117) sad the `include statement could be used. To define a global constant you can use the `define statement into a separate verilog file and than include it where needed in your code. Here is an example:

included_file.v: 


`ifndef INCLUDED_FILE
     `define SIZE 8'd5
`endif
Best regards,

VT