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Altera_Forum
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7 years ago

Verilog Coding

Hello, I'm getting the following error when I'm implementing the below Verilog code. [Synth 8-403] loop limit (65536) exceeded parameter N=10; parameter M=8; parameter depth=(1<<N...
Altera_Forum's avatar
Altera_Forum
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7 years ago

Thanks for your response. It's my mistake.i declared "i" as a single bit.