Verilog Coding

Where is i declared? Probably should be declared as an integer;

Probably like this, with the added text in red:

always@(posedge clk)
    begin : block_name
    integer i;
    if (rst==1'b1)
        begin
        next_sp=0;
        dataout=0;
        for(i=0;i<(depth-1);i=i+1)
            begin
            stack_mem=0;
            end
        end
    end

Note that by requiring that clearing the whole memory in one clock cycle be done, you will be forcing the implementation of stack_mem[] to be done be an array of clearable registers, and not using a block_ram type of memory structure. Hope that is what you intend.

Also clk, rst, next_sp, and dataout need to be declared somewhere (maybe you left out some code ... ?)