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Altera_Forum
Honored Contributor
8 years agoVerilog coding issue
:confused::confused:Hello everyone can some buddy guide me how initialize your own data set in verilog with complete sample example. I have written a code but getting error module mean(A1,A...
Altera_Forum
Honored Contributor
8 years agoWhat error are you getting? You've defined the inputs and outputs as single bit, but it seems like you're trying to create each as a 50 element memory?