--- Quote Start ---
@kaz,
Would a comment, such as the following, be sufficient to address your concerns?
As a first rule, do not drive your logic like this:
always @(posedge counter)
begin
// DON'T DO THIS
end
This will cause you all kinds of grief, either leading you to an unreliable design, or forcing you to deal with multiple clock domains, clock domain transfers, and worse. Unless you really know what you are doing … don’t use this approach.
As for the word "timing", I'm kind of stuck. It does have the specific idiomatic meaning within the context of FPGA's that you state above, but it also has the traditional english meaning (
https://www.google.com/search?client=ubuntu&channel=fs&q=timing&ie=utf-8&oe=utf-8) of:
the choice, judgment, or control of when something should be done.
"one of the secrets of golf is good timing"
a particular point or period of time when something happens.
plural noun: timings
It was this latter meaning I was intending to use. Is there any particular synonymn that you think would be better? "Controlling Sequencing" for example?
Dan
--- Quote End ---
I don't want to pretend I am as good in English as our chief moderator Tricky but I suggest tilte to be "How to Divide clock and how to use the divided clock"
Yes keep clock edge statement clean of any divided clock but follow it by divided clock:
always @(posedge clean_clock)
begin
if divide_clk then //dirty divided clk
...
end
end
Honored Contributor
