--- Quote Start ---
@kaz,
So ... you would recommend I place a comment prior to the "Strobe Signal" section recommending that users not use a "divided" clock to drive their logic?
Dan
--- Quote End ---
For internal fpga logic running at conventional speeds yes do not divide clock to use it as clock as it leads to various hold problems and could upset Rysc. Keep the fast clock and use divided output as clk enable.
For LED control it does not matter at all as LEDs need very slow drive and this is not the main theme for fpga design though it is attractive for tutors and students projects.
Moreover the title of the link is confusing as we normally mean by "timing" the register timing (setup and hold as checked by timing tool). It should be titled "clocking...something"
Honored Contributor
