Forum Discussion
Arno-NL
Occasional Contributor
Occasional ContributorVerilog 2005 Module Synax: No localparam port declaration allowed!
Dear Intel,
It came to my attention when I tried some Verilog code, that Quartus synthesis and Modelsim do not deal with Verilog 2005 in the same way when it comes to defining local parameters in t...
Sent you an email.
ShengN_altera
Super Contributor
Super ContributorSent you an email.
Arno-NLOccasional Contributor
Occasional ContributorHello Sheng N,
The solution you provided through e-mail works sufficiently save the footnote I told about in my email reply. Thank you for assisting with this issue.
Regards,
Arno.
