Verilog | Instantiating a varied parameter

Parameters are constants that are must be known when Quartus is run. Parameters are used in your code that defines what the circuit looks like. This is similar to how# define works in C/C++. What you have calculates the number of 1s and then expects the circuit to change at run time based on that. You could use a parameter for something like the max number of 1s, or the width of signals. You cannot use them for things that are calculated when the circuit is running.