Verilog | Instantiating a varied parameter

You left out the most important part. The [NUMBER OF 1'S CALCULATED] is where the problem is. Please post that.

Keep in mind that parameter values must be known at compile time. You can do calculations with them, but any inputs must be constants or other parameters. They cannot be variables, registers, wires etc. Verilog isn't like software languages. The hardware is created when the FPGA image is built and in general cannot be changed at runtime.