this is my ROM code
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ROM_Venda is
port(address : in std_logic_vector(1 downto 0);
dataOut : out std_logic_vector(7 downto 0));
end ROM_Venda;
architecture RTL of ROM_Venda is
subtype TDataWord is std_logic_vector(7 downto 0);
type TROM is array(0 to 3) of TDataWord;
constant c_memory: TROM := (0 =>"00000000", 1 =>"01010000", 2=>"01100100", 3=> "01111000"); -- Produto 1 ->80 Produto 2 ->100 Produto 3 ->120
begin
process (address)
begin
case address is
when "00" =>
dataOut <= c_memory(0);
when "01" =>
dataOut <= c_memory(1);
when "10" =>
dataOut <= c_memory(2);
when "11" =>
dataOut <= c_memory(3);
end case;
end process;
end RTL;