(vcom-1253) No default binding for component instance "counter : a_74161".

Hi all,

I am trying to simulate a simple counter in model sim using a counter implemented using the a_74161 counter from altera’s maxplus2 library: C:\altera\13.0\quartus\libraries\vhdl\altera

Simulating the design in quartus works fine using the University Program VWF – so the design appears to work - see attachment.

Trying to simulate the counter in multisim I don’t get far: When I compilate my file in multisim:

vcom -reportprogress 300 -bindAtCompile -work work C:/altera/13.0/work_2/z_74161.vhd

I get:

# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package maxplus2# -- Compiling entity z_74161# -- Compiling architecture z_74161_arch of z_74161# ** Warning: [1] C:/altera/13.0/work_2/z_74161.vhd(66): (vcom-1253) No default binding for component instance "counter : a_74161".# (No entity named "a_74161" was found.)

Code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera;

USE altera.maxplus2.ALL;

ENTITY z_74161 IS

port ( clk: in STD_LOGIC;

ldn: in STD_LOGIC;

clrn: in STD_LOGIC;

enp: in STD_LOGIC;

ent: in STD_LOGIC;

d: in STD_LOGIC;

c: in STD_LOGIC;

b: in STD_LOGIC;

a: in STD_LOGIC;

qd: out STD_LOGIC;

qc: out STD_LOGIC;

qb: out STD_LOGIC;

qa: out STD_LOGIC;

rco: out STD_LOGIC);

END z_74161;

ARCHITECTURE z_74161_arch OF z_74161 IS

BEGIN

counter: a_74161

PORT MAP(

clk => clk,

ldn => '1',

clrn => '1',

enp => '1',

ent => '1',

d => '0',

c => '0',

b => '0',

a => '0',

qd => qd,

qc => qc,

qb => qb,

qa => qa,

rco => rco

);

END architecture z_74161_arch;

I have also compiled the “C:\altera\13.0\quartus\libraries\vhdl\altera” into “C:\altera\13.0\work_2\simulation\modelsim\altera” (see attachment).

Any help is appreciated

br /mattias