vcd file output in modelsim altera for power analysis

I am trying to generate vcd file in ModelSim.

For that i followed following steps

1 . Full Compilation of VHDL files ( excluding testbench.vhdl file) in quartus software, with selection of ModelSim Altera in EDA tool and DESIGN INSTANCE NAME as 'testbench' ( which is my testbench file name as well as testbench entity name).

2 The TCL file is copied to the folder where simulation is done using ModelSim, along with all vhdl files (including testbench file) . i am using testbench to do simulation .

3 With this i compiled and simulated the file and then loaded the tcl file using "source address_generator_dump_all_vcd_nodes.tcl " command.

then tried to run the simulation with run 5000 ns;

I expected "address_generator.vcd" file with some information. But

the file doesnot have any content in it before the simulation is closed.

When the simulation is closed, it only contain lines as below

"$date

Tue May 18 15:06:57 2010

$end

$version

ModelSim Version 6.4a

$end

$timescale

1ps

$end

"

I dont know what is the reason that i am not getting data in the vcd files.

Any help is appreciable

With regards

pasa