Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI generally agree with Tricky, that you need to understand better the difference between hardware description language and software programming language.
Nevertheless, your original code can compile when implementing a as a signal. Of course, this doesn't necessarily imply, that it does something reasonable. I don't know the internal operation of the component "test". Your remark about "divide an image in 8x8 blocks" suggests, that you intend to use inpp(a, a) as a kind of pointer to subarray. But it isn't, it's just a single array element. If you mean a range, you have to write a range, e.g. inpp(a to a+7, a to a+7). The correct method to create multiple instances of a component would be a generate statement rather than a loop. But as you already mentioned, it would involve a large resource requirement. The principle alternative is to perform the operation sequentially with a single component instance, which is basically described in your above code. But there's a serious problem. The way you write the code, the array itself isn't but a huge amount of FPGA registers (or unregistered signal wires, depends on). Multiplexing this signals to single component involves even more FPGA resources and most likely won't work with practical array sizes. I suggest, that you start with reviewing some basic image processing VHDL projects and try to understand, how they manage the data path. In most cases, they'll rely on FPGA internal RAM blocks or, in case of larger image arrays, external RAM. Then multiplexing becomes a resonable method. I'm sure, you'll also find text books dedicated to FPGA image processing.