Honored Contributor
Honored ContributorWhat I am doing is to implement the merge sort between two true-dual-port RAMs. RAM1 stored the initial data, and RAM2 is empty at the beginning.
The Merge sort operation need to take two RAM1 data and store to the RAM2 in order after comparison. What I want to do is a component which did take the number and compare operations. And use a state-machine to pass the proper parameters such as the starting location of picking data. At each state the parameter is different, but operation is the same. I have tried to write a very long if elsif statement to achieve the operation but come with a low Fmax and high logic unit usage. Thus I want to write it in a way which only build one component with different input signals at different stage, since all the operations is the same ( pick data -> compare -> store to RAM2) but with different parameters (e.g. starting location of pick data). At each stage, I need to initialize some signals/variables in the process, but I am not sure how to do that. Or is there any better way to do this?
