Forum Discussion
AlexBeasley
Occasional Contributor
Occasional Contributoruvm_config_db fails to get interface UVM QuestaSim
Hi there
I am trying to get a simulation working in QuestaSim - Intel FPGA Edition using UVM.
Below is the design with all the UVM class extensions
`timescale 1ns/1ps
`include "uvm_macro...
The problem has been spotted.
Note: there is a typo in some of theuvm_config_db#()::get()/set()lines, where I have mixed up "des_vif" and "des_if" for the handle!
Totally didn't spot it!
RichardT_altera
Super Contributor
Super ContributorThe fatal error is generated from the tb.sv itself. You might need to check line 274.
