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AlexBeasley's avatar
AlexBeasley
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

uvm_config_db fails to get interface UVM QuestaSim

Hi there I am trying to get a simulation working in QuestaSim - Intel FPGA Edition using UVM. Below is the design with all the UVM class extensions `timescale 1ns/1ps `include "uvm_macro...
  • AlexBeasley's avatar
    AlexBeasley
    4 years ago

    The problem has been spotted.

    Note: there is a typo in some of the 

    uvm_config_db#()::get()/set()

    lines, where I have mixed up "des_vif" and "des_if" for the handle!

    Totally didn't spot it!

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

I am using Questa Intel FPGA Edition-64 2022.1 Revision: 2022.01


I run using the tb.sv provided, along with the command, and does not see any fatal error.


Best Regards,

Richard Tan