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Altera_Forum's avatar
Altera_Forum
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9 years ago

Using TCL (or other Script) file in Quartus to automate module/circuit creation

I have various simple modules (Verilog) written and included in my Quartus project file. Lets say each such module receives a 8 bit input, increments the value and outputs the new value. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

You can create a top level verilog file with the Parameter N, and then set the parameter from project settings.

If you're only interested in simulation at the moment, you can set the parameter when you run the simulation in modelsim using the -g option from the command line:

vsim my_design -gN=8