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Altera_Forum's avatar
Altera_Forum
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15 years ago

Using SignalTap with a device configured by an external processor?

I'm new to SignalTap II and having just been through the online training, it looks as if it only works when configuring the FPGA directly from the PC by JTAG or USB Blaster.

Is there any straightforward way of using SignalTap II with devices that are configured by an external processor?

Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I don't see why configuration method has anything to do with signaltap.

    As long as there is one or more a signaltap instants (as any fpga module), the module should capture data into internal buffer and pass it out thorough fpga jtag port.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As our FPGA is not connected directly to the PC, SignalTap doesn't see the hardware. I guess we would have to write a program on the external processor which would present data generated by the signaltap instance back to the PC. My first thoughts were that this probably isn't worth the effort given that I can always re-write my code to present signals to IO and then view them on a scope. There is a reasonable amount of work involved in this however as we are structuring our code as custom components within SOPC Builder and there are >50 signals we wish to observe.

    Still this is the way I will go, unless someone has gone through the process and knows of e.g. any freeware which would perform this task? Or alternatively if you tried it and found it to be unworthy of the effort, please let me know as well.

    Thanks again
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As kaz says, you can perfectly configure the FPGA with an external CPU, e.g. in Passive Serial mode, while having the USB-blaster connected to the JTAG port. Once you have loaded the logic you can capture events with SignalTap. The SignalTap SW will even detect when you have loaded/configured the FPGA.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Preferably, the embedded firmware would be designed to allow reconfiguration of the FPGA from JTAG port and continue regular operation. Otherwise, the debug configuration including Signaltap must be transferred to the processor first. If several iterations are necessary, it's a longwinded process.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Preferably, the embedded firmware would be designed to allow reconfiguration of the FPGA from JTAG port and continue regular operation.

    --- Quote End ---

    The embedded firmware can only prevent configuration by the JTAG port by holding 'config-' low, but in that case the firmware itself can not load the firmware either ...

    The only restriction could be that the firmware must pause accessing the FPGA while the logic is reloaded via the JTAG port, or that it must be able to recover gracefully when the JTAG loads new logic.

    --- Quote Start ---

    Otherwise, the debug configuration including Signaltap must be transferred to the processor first. If several iterations are necessary, it's a longwinded process.

    --- Quote End ---

    Could you humour us and explain how this would work?