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Preferably, the embedded firmware would be designed to allow reconfiguration of the FPGA from JTAG port and continue regular operation.
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The embedded firmware can only prevent configuration by the JTAG port by holding 'config-' low, but in that case the firmware itself can not load the firmware either ...
The only restriction could be that the firmware must pause accessing the FPGA while the logic is reloaded via the JTAG port, or that it must be able to recover gracefully when the JTAG loads new logic.
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Otherwise, the debug configuration including Signaltap must be transferred to the processor first. If several iterations are necessary, it's a longwinded process.
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Could you humour us and explain how this would work?
Honored Contributor
