Honored ContributorHi all,
I am using a Cyclone 3 FPGA (EP3C16F256) and I want to use it's RAM. I am not familiar with internal RAM on FPGAs, I was going to write it myself as an array but then I found out that it has a internal RAM. Could anyone give me a quick guide about using that RAM? Thanks, Dvido
Honored ContributorIf you're writing HDL code, its normally best to write and array anyway and then let the synthesisor determine how much ram you actually need.
Otherwise, check out the cyclone 3 reference manual http://www.altera.com/literature/hb/cyc3/cyc3_ciii51004.pdfHonored ContributorSo the synthesizer will determine automatically whether to put the array that I wrote as RAM? I don't need to define anything special?
Honored ContributorAslong as you follow the general coding guidlines, yes
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf I dont know anything about verilog, but I know in VHDL Quartus will also let you use arrays of types other than std_logic_vector to infer rams from, including signed/unsigned and integer (thats given a limiting range), and fixed point types in the new IEEE floatfixlib.Honored ContributorAs another point - I think its much better using arrays anyway as its a bit more clear whats going on than connecting signals into a port map!
Honored ContributorA shortcut to learn the RAM inference syntax is to use the respective VHDL templates offered by the Quartus editor context menu.
