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I mean is since after power on the FPGA, we will see the "lock" be low, then goes high later. So we will never see the lock signal has a falling edge if we don't reset the PLL.
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The negedge statement is so the Verilog understands you are using the signal as an asynchronous reset. It does not matter if there actually is a negedge.
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Is this command synthesisable which make the signal q be "0" after power (don't need to do reset)? Or is this just for simulation?
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This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream.
Cheers,
Dave
Honored Contributor
