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Honored Contributor
Honored ContributorUsing PLL "lock" signal as the async reset in Verilog
If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "loc...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I mean is since after power on the FPGA, we will see the "lock" be low, then goes high later. So we will never see the lock signal has a falling edge if we don't reset the PLL. --- Quote End --- The negedge statement is so the Verilog understands you are using the signal as an asynchronous reset. It does not matter if there actually is a negedge. --- Quote Start --- Is this command synthesisable which make the signal q be "0" after power (don't need to do reset)? Or is this just for simulation? --- Quote End --- This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream. Cheers, Dave
