Using PLL "lock" signal as the async reset in Verilog

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Yes. For example, lets say you have an external reset (from a reset supervisor) and your PLL lock signal. A simple register would be ...

assign rstN = lock & ext_rstN;
always @ (posedge clk or negedge rstN)
if (~rstN) 
   q <= 1'b0;
else 
   q <= d;

However, keep in mind that you would normally want to synchronize the reset source to each clock domain, i.e., rstN should be synchronized to clk, otherwise you will run into reset timing issues.

Cheers,

Dave

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Thanks very much, Dave. Yes, I need to synchronize the reset otherswise I may have problem in reset deassert.

The example you took is a little different from what I mentioned since the " external reset " will have the falling edge. But just assume I don't have this external reset, I only have "lock" signal as the reset and I won't have falling edge in normal case, can I still put :

negedge lock into the always sensitive list?

Or ask in anther way, if there is only low voltage level in "lock", there is no falling edge, whether this lock signal can still trigger the reset or not?

Thanks very much.