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Altera_Forum's avatar
Altera_Forum
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12 years ago

Using PLL "lock" signal as the async reset in Verilog

If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "loc...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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Let's assume the lock from PLL is a clean signal. Can I write the verilog code as my previous post?

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Yes. For example, lets say you have an external reset (from a reset supervisor) and your PLL lock signal. A simple register would be ... 


assign rstN = lock & ext_rstN;
always @ (posedge clk or negedge rstN)
if (~rstN) 
   q <= 1'b0;
else 
   q <= d;

However, keep in mind that you would normally want to synchronize the reset source to each clock domain, i.e., rstN should be synchronized to clk, otherwise you will run into reset timing issues.

Cheers,

Dave