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Altera_Forum
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11 years ago

Using multiple BFMs in VHDL / Problems with use clauses

Hi. I'm trying to create a VHDL testbench using Altera Verification BFMs. The DUT has an Avalon-MM Slave Interface, an Avalon-ST Sink Interface and an Avalon-ST Source Interface. The gener...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I made it work the "dumb" way:

>Include all altera_BFM libraries and use clauses for the testbench entity

>Rename the conflicting signals (such as req_if) or functions in the BFMs files (altera_avalon_master_bfm_vhdl_*, etc) so the compiler will know exactly which one you're calling

>Done

It's a workaround, I still don't know why ModelSim won't allow me to restrain the use clauses to specific processes or to use the functions with the syntax library.package.function().