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Any other suggestions towards my code? How about the fact that the IOs are asynchronous input. I am not taking any precautions because they don't change 'that' often.
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I assumed that your input clock is derived from processor clock, in this case all bus signals are actually synchronous, you have to observe setup and hold times however.
If the bus signals are unrelated to clk, reliable operation can't be expected.
As I already mentioned,
we simply have to assume, that the interface is cooperating correctly with coldfire bus signals. You have to check this.
P.S.: The latter is also my comment on your last question. The FSM as such has no race conditions, as far as I see. But this doesn't guarantee correct timing of bus signals. I don't know the respective requirements and can't suggest a solution.
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