Using FPGA to map I/Os into address space

Any other suggestions towards my code? How about the fact that the IOs are asynchronous input. I am not taking any precautions because they don't change 'that' often. They report the status of some other device or some control signals to these devices. Any problem with that? In my simulation, there's some delay between when the register value is set and the corresponding IO lines change reflecting the change in register. I guess this is because I did't fully constrain the design. If to properly constrain the design, what timing constrain do I need besides the obvious 80MHz input clock signal from coldfire?

Thanks

Also about the FSM. To keep the clairty of the code, I prefer to keep the three processes structure. Therefore I am little bit concern about possible racing condition. I have the first process advancing the FSM on the rising edge of clock. However, my third process of the FSM generating the outputs based on the CURRENT STATE also updating on rising edge. Wouldn't this create potential race condition for me? The only way I see to solve this is to use a falling edge fir one of the two processes. Is it so? If so, it looks like some of the Dffs launching edge and latch edge are inverted of each other, resulting only half the clock in betwen. This create problem for me. Anyone can explain to me?